The Fault-Tolerant Quantum Computing roadmap aims for a full-stack scalable quantum computing system, including the qubit circuits, the control electronics, and the software layers such as compilers. The approach to achieve fault tolerance is based on quantum error correction, in which information is encoded redundantly enabling error detection without destroying quantum data. The qubit hardware systems are electron spins in quantum dots and superconducting quantum circuits.
Quantum error correction is a necessity for achieving scalable universal quantum computation. In a quantum error correcting code, quantum information is distributed among many elementary degrees of freedom, qubits, so that the dominant noise processes affect this information in a reversible manner. This means that there exists an error reversal procedure by which one can detect and correct the errors. The choice of how to represent the quantum information as entangled states of many elementary qubits is made through the choice of quantum error correcting code.
The most viable class of codes for 2D solid-state hardware are surface codes. Such codes use a 2D array of elementary data qubits which stores the quantum information. In addition ancilla or helper qubits are placed near the data qubits to collect information about errors. In one quantum error correction cycle ancilla qubits are coupled to the data qubits and pick up information about the data qubits in the form of parity checks.
Errors due to decoherence or faulty gates affect the values of these parity checks, thus allowing errors to be detected and corrected. Classical feedback electronics analyzes the parity check signals and issue all corrective actions. The smallest circuits for demonstration of surface coding require 13 or 17 qubits.
We pursue the realization of (surface) codes with two approaches : superconducting qubits and electron spin qubits in quantum dots. Superconducting quantum processors with five qubits are already operational, with basic gate, readout and feedback operations demonstrated. The current emphasis is on maximizing the multiplexing of control technology to allow double-digit qubit numbers, while keeping high fidelity in all operations. The overall goal with quantum dot spin qubits is to demonstrate and exploit millisecond coherence and qubit control, initialization and readout at 99.9% fidelity in a surface-code compatible architecture. Besides these hardware efforts theoretical research in this roadmap focuses on developing a scalable computer architecture based on surface code hardware as well as on developing more hardware-efficient and hardware-adapted quantum error correction.
We have started a close collaboration with Intel Corporation in 2015 bringing highly complementary expertise to our efforts. This collaborative project focuses on spin qubits in quantum dots, superconducting qubits, cryogenic control electronics, the qubit-electronic interface and quantum computer architecture (see https://qutech.nl/qutechentersintocollaborationwithintel/). We also work closely with suppliers of test and measurement electronics and cryogenic equipment.
For more information, please check out the individual sites of labs and groups in this roadmap.
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